1. Field of the Invention
The present invention relates an apparatus and a method for generating a CMOS model and particularly to CMOS model generating apparatus and method for generating a CMOS model taking distributions of variation in an n-channel MOS transistor and a p-channel MOS transistor suitable for Monte Carlo analysis into account. The present invention also relates to a CMOS model generating program of such a CMOS model generating method and a recording medium storing this CMOS model generating program.
2. Description of the Related Art
Transistors to be integrated into an integrated circuit, e.g. an n-channel MOS transistor (hereinafter, abbreviated as “nMOS”) and a p-channel MOS transistor (hereinafter, abbreviated as “pMOS”) of a CMOS (Complementary Metal Oxide Semiconductor) are known to have various characteristics that vary between chips of a wafer or in the chips (see, for example, Non-Patent Literature 1).
FIG. 4 are graphs showing voltage-current characteristics between sources and drains of MOS transistors. FIG. 4A is a graph showing the voltage-current characteristics between the source and drain of an nMOS and FIG. 4B is a graph showing the voltage-current characteristics between the source and drain of a pMOS. Horizontal axes of FIG. 4 represent drain voltage Vd and vertical axes represent drain current Id. It is assumed that the polarity of voltages and currents relating to the pMOS is opposite to that relating to the nMOS. FIG. 5 are scatter diagrams showing a correlation of a saturation current of the nMOS and that of the pMOS. FIG. 5A shows the result of actual measurements and FIG. 5B shows points FF, SS, FS, SF and TT. Here, suffix n indicates the case of the nMOS and suffix p indicates the case of the pMOS.
As shown in FIG. 4, the voltage-current characteristics between the sources and drains of the nMOS and pMOS (hereinafter, abbreviated as “voltage-current characteristics”) are changes of the drain currents Id flowing between the sources and drains in relation to changes of the drain voltages Vd between the sources and drains in the case of applying a specified constant gate voltage Vg between the sources and gates. The voltage-current characteristics roughly have such profiles that the drain current Id saturates at a substantially constant level after linearly increasing as the drain voltage Vd increases. The voltage-current characteristics having such profiles vary from a characteristic with a small drain current Id (hereinafter, called “Slow”) to a characteristic with a large drain current Id (hereinafter, called “Fast”) due to variations of production conditions even if the same gate voltage Vg is applied as shown in FIG. 4. Such Slow and Fast are characteristics with smaller occurrence frequencies than a statistical representative value (average value, median, etc.), specify the limits of variations, and are generally called “corners”. In the Fast, the response speed is relatively fast since the drain current Id is large. In the Slow, the response speed is relatively slow since the drain current Id is relatively small.
Actually, various characteristics exist from Slow to Fast, but only Slow, Fast and Typical are shown, but the others are not shown in FIG. 4. This Typical is a typical voltage-current characteristic with a largest occurrence frequency that can be a statistical representative value. Vnd and Ind denote the drain voltage Vd and the drain current Id of the nMOS, and Vpd and Ipd denote the drain voltage Vd and the drain current Id of the pMOS. The drain current Id in the case where the voltage-current characteristic saturates is called a saturation current I; InS, InF and InT denote the saturation currents In of the Slow, Fast and Typical of the nMOS; and IpS, IpF and IpT denote the saturation currents Ip of the Slow, Fast and Typical of the pMOS. Of course, relationships InS<InT<InF and IpS<IpT<IpF hold.
In a CMOS including the nMOS and pMOS, the voltage-current characteristics of the nMOS and pMOS vary and there is a correlation between the nMOS and the pMOS. Thus, in an In-Ip space defined by the saturation current In of the nMOS and the saturation current Ip of the pMOS with a horizontal axis representing the saturation In of the nMOS and a vertical axis representing the saturation Ip of the pMOS, a relationship between the saturation current In of the nMOS and the saturation current Ip of the pMOS is as shown in a distribution scatter diagram of FIG. 5.
Thus, in the case of designing a CMOS integrated circuit, a designer simulates characteristics of the designed integrated circuit using a circuit simulator such as a SPICE (Simulation Program with Integrated Circuited Emphasis) in order to obtain a chip satisfying a specified specification and to ensure a sufficient yield rate. The designer has to consider such variations of the nMOS and pMOS constituting the CMOS. To this end, the characteristics may be guaranteed by simulating the respective points in the scatter diagram shown in FIG. 5A, but this method is difficult since it is difficult to statistically generate the respective points of the scatter diagram shown in FIG. 5A and there is no method for converting the points into model parameters in the original SPICE even if these points could be determined. Thus, conventionally, the characteristics have been guaranteed by performing simulations for corner chips (worst cases chips) and a typical chip shown in FIG. 5A. Specifically, as shown in FIG. 5B, for the respective cases of a state FF where the response speeds of the nMOS and pMOS are both fast (corner condition FF), a state SS where the response speeds of the nMOS and pMOS are both slow (corner condition SS), a state FS where the response speed of nMOS is fast and that of the pMOS is slow (corner condition FS), a state SF where the response speed of nMOS is slow and that of pMOS is fast (corner condition SF) and a state TT where the response speeds of the nMOS and pMOS are both typical (typical condition TT), the values of parameters in device models of the nMOS and pMOS generated for the circuit simulation have been transmitted from a production side (processing department) to a design side, and the characteristics of the designed integrated circuit have been simulated using these values of parameters to guarantee the characteristics. Such a design method is called a worst design technique and disclosed, for example, in Patent Literature 1 and Non-Patent Literature 2.
Since the characteristics of the integrated circuit are evaluated for the five states, i.e. the above corner conditions FF, SS, FS and SF and the typical condition TT shown in FIG. 5B according to the background art, these evaluations do not take the distributions of variation in the nMOS and pMOS into account and these five states are discrete. Therefore, it is not possible to obtain a distribution of variation in the characteristic of the integrated circuit.
Particularly, in integrated circuits produced by a fine process of the recent years, all the nMOSs and pMOSs do not vary toward the same corner and the nMOSs and pMOSs vary in various manners as shown in FIG. 5A. Thus, the characteristic of the integrated circuit needs to be evaluated in consideration of the distributions of characteristic variation in the nMOSs and pMOSs. Particularly, since targets of the characteristics are diverse and continuous in the design of analog circuits, whether or not the design is good is judged not only by the characteristics at the corners as in the design of digital circuits, but by referring to the continuous distributions of the characteristics in many cases. Therefore, it is important to obtain the distributions of characteristic variation.
[Patent Literature 1]